FIELD OF THE INVENTION
The invention relates to a semiconductor memory containing word and bit lines and also memory cells connected thereto. A signal path is formed which contains one of the memory cells, the word and bit lines connected to the memory cell, and also circuit elements, in order to write a data value from an external terminal of the semiconductor memory to the memory cell or to output the data value from the memory cell to the external terminal. A control device is further provided and generates control signals for driving the signal path.
Integrated semiconductor memories, for example so-called dynamic random access memories (DRAMs), contain a memory cell array with a multiplicity of mutually crossing word and bit lines. The memory cells are in each case disposed at the crossover points between a word line and a bit line and are connected thereto. The word line activates an access to the memory cell, while a data value is read out or written to the memory cell via the bit line. The word lines are driven by a word line decoder that selects at least one word line from the multiplicity of word lines in a manner dependent on an address. The bit lines are usually connected in pairs as bit lines carrying complementary data signals to a primary sense amplifier. The primary sense amplifier amplifies a data value that originates from that memory cell whose word line is activated. By way of example, all the primary sense amplifiers of the memory cell array provide such a data value. Afterward, one of the sense amplifiers is selected by a bit line decoder in order to forward its data value to a secondary sense amplifier. The secondary sense amplifier outputs the data signal to be read out with sufficient amplification to further signal lines which are connected to a data output terminal of the semiconductor memory. The data can be tapped off externally at the data output terminal. Conversely, an input signal applied to the data output terminal is written to a memory cell selected via a word line decoder and a bit line decoder. All the control measures of the signal path described are monitored by a control device. Depending on commands applied to the control device, on the output side a multiplicity of control signals are generated which activate and deactivate again the respective functional units of the signal path for writing and for reading data values with correct timing.
In conventional DRAMs, write accesses and read accesses are controlled internally within the module by a fixed sequence of control signals. By way of example, the internal control signals follow the commands, usually applied externally by a memory controller, as quickly as possible. In many cases, a signal is also delayed with a fixedly predetermined time in order to be provided in a correctly timed manner. The internal signal processing is fixedly dependent on the configured circuit and can no longer be altered subsequently.
Owing to the advancing miniaturization of the components on account of ever smaller structure widths that can be fabricated in the integrated fabrication process, a module configuration is repeatedly adapted to new fabrication processes. The predictability of the signal propagation times and of the switching times of the functional elements proceeding from a circuit configuration that is transferred to a new fabrication process therefore becomes problematic. Moreover, variations in the electrical parameters are established anyway on account of fluctuations in the fabrication process. This can have the effect that the functional properties of the same configuration deviate from one another and, in the extreme case, even the entire semiconductor memory must be assessed as non-functional. Since the market for semiconductor memories is short-lived and innovations have to be implemented as quickly as possible, an adaptation of the configuration or of the circuit layout would delay the availability of a new semiconductor memory to an undesirable extent.
It is accordingly an object of the invention to provide a semiconductor memory with a signal path that overcomes the above-mentioned disadvantages of the prior art devices of this general type, which can be adapted more quickly to changes in the fabrication process while adhering to the same electrical functionality.
With the foregoing and other objects in view there is provided, in accordance with the invention, a semiconductor memory. The memory contains word lines, bit lines crossing the word lines, memory cells each connected to a word line and a bit line, and a signal path. The signal path contains a respective memory cell of the memory cells, the word line and the bit line connected to the respective memory cells, an output terminal, and circuit elements for writing a data value present at the output terminal to the respective memory cell or to output the data value from the respective memory cell to the output terminal. A control device is provided for generating control signals for activating and deactivating the circuit elements of the signal path. At least one delay circuit with an adjustable signal delay to accelerate or to delay at least one of the control signals with the adjustable delay time. The delay circuit is connected between the control device and at least one of the circuit elements.
The invention provides for the control signals which drive the functional units of the signal path for read-in or read-out purposes to be provided with an adjustable, preferably irreversibly programmable delay time. Therefore, after the conversion of a configuration to a new fabrication process, the respective delay time of the affected control signals can be adapted. Both a delay and an acceleration are conceivable. In the sense of the invention, a programmable delay also includes an acceleration of the propagation of a signal along a signal path. Moreover, when testing an individual semiconductor module, the internal signal propagation times thereof can be set finely in order to compensate for parameter variations on account of fluctuations in the fabrication process. Consequently, an identical or only slightly altered configuration can be produced relatively quickly in a new semiconductor process. A separate simulation of the semiconductor module, which would require many different conditions and safety margins for critical signals, is no longer necessary to this high degree. Rather, there is adaptation, if appropriate individually for each module, of the relationship of signal propagation times within the semiconductor memory in the core area of the memory.
The adaptation can be set reversibly and by a so-called soft set or irreversibly by permanent programming of a so-called fuse or antifuse. All the control signals that are relevant when reading in or reading out data can be individually delayed or accelerated in this way.
By way of example, the signal path whose control signals are to be adapted contains all the circuit elements in order to write a data value present at an external terminal, a pin, of the semiconductor memory to one of the memory cells or to output a data value from the memory cell to such an output terminal. The circuit elements of the signal path are controlled by the control device outputting control signals in order to be activated or deactivated, that is to say to be enabled or blocked. The signal path contains for example a word line decoder, in order to select at least one of the word lines from the multiplicity of word lines disposed in the memory cell array. The word line decoder is enabled by a corresponding control signal that is generated by the control device. Now, according to the invention, a delay circuit whose delay time can be set reversibly or irreversibly, is connected between the relevant output of the control device and the corresponding enable input of the word line decoder. In this case, a delay time also refers to a possible acceleration of the signal propagation time relative to a preset initial state. Furthermore, the signal path contains a primary sense amplifier to which at least one of the bit lines is connected. The primary sense amplifier is again activated and deactivated by at least one control signal. A secondary sense amplifier is connected downstream of a multiplicity of primary sense amplifiers and selects one of the multiplicity of data signals of the memory cell array that are offered by the primary sense amplifiers. Both the selection circuit, the so-called bit line decoder, and the secondary sense amplifier itself can be activated and deactivated by respective control signals.
Semiconductor memories are conventionally provided with bit lines that carry complementary signals and are jointly connected to a primary sense amplifier. Before a read-in or read-out operation, a potential of the bit lines among one another is equalized by the bit lines being short-circuited. In a refinement of the invention, the control signal provided by the superordinate control device is accelerated or delayed in a programmable manner along the signal line from the control device to the equalization transistor.
Various possibilities are conceivable as an embodiment of one of the multiplicity of delay circuits for the respective control signals. Thus, on the one hand, it is possible to provide a conventional delay line that contains, for example, two cascaded inverters and is connected in series with a programmable switch. Connected in parallel with that is a switchable signal line without such a delay path. The two switches are embodied in a complementarily controllable manner, for example as transfer gates. Thus, either the signal path containing the delay elements is switched on and delays the signal on the way from the control device to the functional unit of the data signal path that is to be controlled. On the other hand, the delay path can be switched off and the faster signal path containing no such delay path is switched on.
As an alternative, a capacitive element connected to the respective signal line carrying the control signal is suitable for the signal delay. The capacitive element contains, for example, complementary MOS field-effect transistors whose gate terminals are interconnected and whose controlled current paths are connected to one another via an inverter. The gate terminals are additionally coupled to the signal line. The input terminal of the inverter that connects the two transistors is finally driven by the programmable element, either a fuse or a soft set register. Depending on the switching state of the programmable element, the capacitance becomes active and modulates an edge of the signal transmitted on the line or remains inactive.
An acceleration of a signal can be achieved by an inverter additionally being connected into the signal line that transmits a control signal. By way of example, the signal line is connected to the input of the inverter and is tapped off from the output of the inverter. The inverter is connected to the supply terminals via respective complementary transistors. If the transistors are switched on, the signal line has an increased driver capability. If the transistors are switched off, the inverter is not active and the line has only a low driver capability. In this way, it is possible either to reduce or increase the delay time along the signal line depending on the presetting of the additional inverter.
All the embodiments of the delay element described can be driven by a soft set register or by a fuse latch. The soft set register has a data value written to it during operation, for example in the course of the initialization of the semiconductor module, and sets the respective switches that are active in the delay element. A fuse latch contains a programmable element, a so-called fuse, which is permanently, irreversibly programmable. The fuse is conducting in the initial state and non-conducting in the programmed state. Nevertheless, it is also possible to use an antifuse that is non-conducting in the initial state and is conducting in the programmed state. The circuitry of the fuse/antifuse provides either a high level or a low level, between which a changeover is made in each case by programming. The logic level output by the programmed or non-programmed fuse is finally read into a memory element that sets the switches that are active in the delay element.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a semiconductor memory with a signal path, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.